1. Field of the Invention
The present invention relates to integrated circuits (ICs) such as field programmable gate arrays (FPGAs). More specifically, the present invention relates to methods for converting FPGAs into standard cell integrated circuits.
2. Discussion of Related Art
FIG. 1 is a simplified schematic diagram of a conventional FPGA 110. FPGA 110 includes user logic circuits such as input/output blocks (IOBs) 160, configurable logic blocks (CLBs) 150, and programmable interconnect 130, which contains programmable switch matrices (PSMs). Each IOB 160 includes a bonding pad (not shown) to connect the various user logic circuits to pins (not shown) of FPGA 110. Some FPGAs separate the bonding pad from the IOB and may include multiple IOBs for each bonding pad. Each IOB 160 and CLB 150 can be configured through configuration port 120 to perform a variety of functions. Configuration port 120 is typically coupled to external pins of FPGA 110 through various bonding pads to provide an interface for external configuration devices to program the FPGA. Programmable interconnect 130 can be configured to provide electrical connections between the various CLBs and IOBs by configuring the PSMs and other programmable interconnect points (PIPS, not shown) through configuration port 120. IOBs can be configured to drive output signals to the corresponding pin of the FPGA, to receive input signals from the corresponding pins of FPGA 110, or to be bi-directional.
FPGA 110 also includes dedicated internal logic. Dedicated internal logic performs specific functions and can only be minimally configured by a user. Configuration port 120 is one example of dedicated internal logic. Other examples may include dedicated clock nets (not shown), delay lock loops (DLL) 180, block RAM (not shown), power distribution grids (not shown), and boundary scan logic 170 (i.e. IEEE Boundary Scan Standard 1149.1, not shown).
FPGA 110 is illustrated with 16 CLBs, 16 IOBs, and 9 PSMs for clarity only. Actual FPGAs may contain thousands of CLBs, thousands of PSMs, hundreds of IOBs, and hundreds of pads. Furthermore, FPGA 110 is not drawn to scale. For example, a typical pad in an IOB may occupy more area than a CLB, or PSM. The ratio of the number of CLBs, IOBs, PSMs, and pads can also vary.
FPGA 110 also includes dedicated configuration logic circuits to program the user logic circuits. Specifically, each CLB, IOB, and PSM contains a configuration memory (not shown) which must be configured before each CLB, IOB, or PSM can perform a specified function. Typically, the configuration memories within an FPGA use static random access memory (SRAM) cells. The configuration memories of FPGA 110 are connected by a configuration structure (not shown) to configuration port 120 through a configuration access port (CAP) 125. A configuration port (a set of pins used during the configuration process) provides an interface for external configuration devices to program the FPGA. The configuration memories are typically arranged in rows and columns. The columns are loaded from a frame register which is in turn sequentially loaded from one or more sequential bitstreams. (The frame register is part of the configuration structure referenced above.) In FPGA 110, configuration access port 125 is essentially a bus access point that provides access from configuration port 120 to the configuration structure of FPGA 110.
FIG. 2 illustrates a conventional method used to configure FPGA 110. Specifically, FPGA 110 is coupled to a configuration device 230, such as a serial programmable read only memory (SPROM), an electrically programmable read only memory (EPROM), or a microprocessor. Configuration port 120 receives configuration data, usually in the form of a configuration bitstream, from configuration device 230. Typically, configuration port 120 contains a set of mode pins, a clock pin and a configuration data input pin. Configuration data from configuration device 230 is typically transferred serially to FPGA 110 through a configuration data input pin. In some embodiments of FPGA 110, configuration port 120 comprises a set of configuration data input pins to increase the data transfer rate between configuration device 230 and FPGA 110 by transferring data in parallel. Further, some FPGAs allow configuration through a boundary scan chain. Specific examples for configuring various FPGAs can be found on pages 4-46 to 4-59 of xe2x80x9cThe Programmable Logic Data Bookxe2x80x9d, published in January, 1998 by Xilinx, Inc., and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference.
Design engineers incorporate FPGAs into systems due to the flexibility provided by an FPGA. Because FPGAs are programmable and re-programmable, a design engineer can easily accommodate changes to the system specification, correct errors in the system, or make improvements to the system by reprogramming the FPGA. However, once the system design is complete, the flexibility provided by the programmability of an FPGA is sometimes not required. Furthermore, because FPGAs are relatively costly ICs and FPGAs require a configuration device which also increases cost, mass produced systems may not tolerate the cost of including FPGAs. Thus, in some systems that are mass produced, FPGAs used in the design phase of the system are replaced by less costly integrated circuits.
Most FPGA manufacturers provide a method to convert an FPGA design into a less costly integrated circuits. For example, some FPGA manufacturers replace the programmable elements of an FPGA with metal connections based on the design file of the FPGA to produce a mask programmed IC. All other circuitry remains the same between the mask programmed IC and the FPGA. The mask programmed IC is cheaper to manufacture than the FPGA and eliminates the need for the configuration device in the mass produced system. However, the mask programmed IC may still be more costly than desired because the semiconductor area, which is a major factor in the cost of an IC, required by the mask programmed IC is nearly the same as the FPGA. Consequently, the manufacturing cost of the mask programmed IC is not significantly cheaper than the FPGA.
Some manufacturers use a xe2x80x9csea-of-gatesxe2x80x9d approach to map an FPGA design into an application specific integrated circuit (ASIC). Specifically, the used CLBs, IOBs, memory cells, and programmable interconnect logic of the FPGA are mapped into corresponding areas of a gate array base. See for example U.S. Pat. No. 5,550,839 entitled xe2x80x9cMask-Programmed Integrated Circuits Having Timing and Logic Compatibility to User-Configured Logic Arraysxe2x80x9d and U.S. Pat. No. 5,815,405 entitled xe2x80x9cMethod and Apparatus for Converting a Programmable Logic Device Representation of a circuit into a second representation of the circuit.xe2x80x9d However, xe2x80x9csea-of-gatesxe2x80x9d gate arrays are not well suited to reproduce the extensive routing and other circuits available in an FPGA. Thus, gate array implementation of FPGA designs may prove costly for FPGA designs requiring extensive routing. Hence, there is a need for a method and structure to convert an FPGA design into an integrated circuit which minimizes the cost of the integrated circuit by reducing the size of the integrated circuit.
The present invention replaces FPGAs with cost effective reduced FPGAs (RFPGAs) for high volume production. Specifically, the present invention uses a completed FPGA design file to design a specific RFPGA with all the functionality of the FPGA design. However, the resulting RFPGA can be manufactured using standard cell techniques which greatly reduces the cost of the RFPGA as compared to the FPGA. Furthermore, the present invention minimizes the semiconductor area of the RFPGA which further reduces the cost of the RFPGA. Additionally, the RFPGA can allow device package changes to further reduce the cost of the RFPGA.
Specifically, in one embodiment of the present invention, models for the configured configurable logic blocks (CLBs), input/output blocks (IOBs), and programmable switch matrices (PSMs) are extracted from the FPGA design file. Then, a reduced logic block (RLB) model is created for each CLB model. Similarly, a reduced input/output block (RIOB) model is created for each IOB model, and a routing matrix (RM) model is created for each PSM model. Additionally, used dedicated internal logic such as block RAMs and boundary scan are extracted from the FPGA and models for each instance are instantiated into the RPFGA.
Specifically, in one embodiment of the present invention, the RFGPA includes a non-uniform array of logic blocks surrounded by a plurality of input/output blocks. An interconnect structure having a plurality of routing matrices connects the various logic blocks within the non-uniform array of logic blocks. The logic block of the non-uniform array of logic blocks are reduced logic blocks which correspond to the configurable logic blocks of an FPGA design. Similarly, the input/output blocks are reduced versions of the IOBs of the FPGA design.
In accordance with another embodiment of the present invention, an integrated circuit includes a first plurality of logic circuits, a routing ring surrounding the first plurality of logic circuits, and a second plurality of logic circuits outside the routing ring. The routing ring has an internal routing grid and an external routing grid. The pitch of the internal routing grid and the external routing grid may differ. The first plurality of logic circuits are placed on the internal routing grid while the second plurality of logic circuits are placed on the external routing grid. The routing ring may include a plurality of wires each having a first endpoint on the internal routing grid and a second endpoint on the external routing grid.
Furthermore, many embodiments of the present invention control timing of the RFPGA. For example, after the RFPGA model is created, the timing characteristics of the RFPGA are extracted and compared to various signal timing constraints. The signal paths which do not satisfy the signal timing constraints are modified to satisfy the signal timing constraints. For example, additional timing buffers or vias may be added to a signal path to increase the timing delay of the signal path. Alternatively, the signal path may be rerouted to decrease the timing delay.
Because creation of RLB and RIOB models can be very time consuming, some embodiments of the present invention use a CLB and IOB database to reduce the time required to create the RFPGA. Specifically, a CLB database would contain corresponding RLB models for particular CLB models. If the CLB database does not include a corresponding RLB model, a new RLB model is created and stored in the CLB database. The IOB database would work in a similar manner.
The present invention will be more fully understood in view of the following description and drawings.